A technique of ball grid array package has been widely used to package integrated circuit chips (IC chips) to form IC components. In a ball grid array package, a solder ball array is formed at the bottom of a package substrate of an IC component, and the solder balls can serve as contacts so that the IC component can be electrically connected to a printed circuit board. Furthermore, signal transmission between the IC chip and the printed circuit board can be established through the solder balls of the solder ball array.
Currently, in the designs of the printed circuit board and the ball grid array, ground balls are electrically connected to a ground plane of the printed circuit board respectively through ground vias, and power balls are electrically connected to a power plane of the printed circuit board respectively through power vias.
In order to reduce voltage drop (or IR drop) due to parasitic resistance of the printed circuit board, the numbers of the ground balls and the power balls are increased as much as possible so as to increase current paths. Accordingly, the numbers of the ground vias and the power vias are increased with the increasing numbers of the ground balls and the power balls, such that the arrangements of the ground vias and the power vias become denser. In addition, the conventional ground and power balls are respectively arranged in different regions to simplify the fabrication of wiring layers of the printed circuit board.
However, parasitic inductance would be easily generated among the ground vias (or the power vias) which are closely arranged. Since transient current variation and parasitic inductance that are generated during the operation of the IC component may result in simultaneous switching noise (SSN) in the circuit, the supply voltage of the IC component would be decreased.
With increasing demand for higher operating efficiency of the IC component, the IC component switches from a low power state to a high power state in a few nanoseconds, and the supply current of the IC component is significantly increased within a very short period of time. The significant increase of the transient current variation magnifies the negative effect caused by the parasitic inductance. That is to say, voltage drop of the supply voltage is increased with the significant increase of the transient current variation and the existence of the parasitic inductance. As such, the power integrity would be reduced, thereby decreasing the operating stability of the electronic device.